In very deep sub-micron designs, integrated circuit manufacturers are starting to see more defects that are not caught by traditional stuck-at-fault testing. Defects like high impedance metal, high impedance shorts, cross talk that may not be caught by traditional stuck at scan vectors show up as timing failures that are caught by at-speed testing.
Running a small number of functional vectors can be time consuming and may produce poor coverage. At speed testing can include transition delay testing and path delay testing. Both generate scan patterns that can be scanned in at a slow speed. After a scan vector is scanned in, two or more capture clocks can be applied at full speed and the captured result can be scanned out, usually at slow speed.
In 90 nm and below, at-speed testing is preferable to ensure good-quality. Relying on ATE for at-speed capture pulses does not guarantee good yield for the needed tester accuracy in high speed integrated circuits. It is also possible that because of testing inaccuracy some good parts would fail the at-speed test.
Multiple clock frequency further complicate matters. For example, in a design with one clock running at 125 MHz and another clock running at 200 MHz, two different capture windows are present. Sometimes, the testing will not support all the required capture pulses at the different frequencies.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.